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Effects of Dielectric Constant on the Performance of a Gate All Around InAs Nanowire Transistor

Identifieur interne : 001D56 ( Main/Repository ); précédent : 001D55; suivant : 001D57

Effects of Dielectric Constant on the Performance of a Gate All Around InAs Nanowire Transistor

Auteurs : RBID : Pascal:12-0087525

Descripteurs français

Pascal (Inist)
- Evaluation performance, Nanoélectronique, Transconductance, Commutation, Temps retard, Dissipation énergie, Effet tunnel, Hauteur barrière, Capacité électrique, Effet quantique, Seuil tension, Tension de grille, Régime hors équilibre, Fonction Green, Arséniure d'indium, Oxyde de silicium, Diélectrique permittivité élevée, SiO2.

English descriptors

KwdEn :
- Barrier height, Capacitance, Delay time, Energy dissipation, Gate voltage, Green function, High k dielectric, Indium arsenides, Nanoelectronics, Non equilibrium conditions, Performance evaluation, Quantum effect, Silicon oxides, Switching, Transconductance, Tunnel effect, Voltage threshold.

Abstract

The effects of gate dielectric constant on the performance of a gate all around indium arsenide (InAs) nanowire transistor are studied using a 3-D quantum simulation. The replacement of SiO₂ by a high-κ dielectric improves the OFF-state current, the ON-state current, the ON/OFF current ratio, the inverse subthreshold slope, the channel transconductance, and the switching delay and degrades the power-delay product. The OFF-state current is mainly tunneling current and the high-κ gate dielectrics improve the device OFF-state performance by increasing the tunnel barrier length. On the other hand, the ON-state current is mainly thermal current and the high-κ dielectrics improve the device ON-state performance by reducing the barrier height. The gate capacitance is increased with high-κ dielectrics. However, the improved ON-state current with high-κ dielectrics makes the switching delay shorter and increases the power (V_DDI_ON) dissipation and power-delay product. Due to very small effective mass of electron in InAs, the quantum effect on threshold voltage is strong and the device with smaller cross section shows better ON-OFF and switching performance at the same gate overdrive voltage.

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to stream Main, to step Corpus: 002206

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Pascal:12-0087525

Le document en format XML

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<author><name sortKey="Alam, Khairul" uniqKey="Alam K">Khairul Alam</name>
<affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Department of Electrical and Electronic Engineering, East West University</s1>
<s2>Dhaka 1212</s2>
<s3>BGD</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
</inist:fA14>
<country>Bangladesh</country>
<wicri:noRegion>Dhaka 1212</wicri:noRegion>
</affiliation>
</author>
<author><name sortKey="Abu Abdullah, Md" uniqKey="Abu Abdullah M">Md. Abu Abdullah</name>
<affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Department of Electrical and Electronic Engineering, East West University</s1>
<s2>Dhaka 1212</s2>
<s3>BGD</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
</inist:fA14>
<country>Bangladesh</country>
<wicri:noRegion>Dhaka 1212</wicri:noRegion>
</affiliation>
</author>
</titleStmt>
<publicationStmt><idno type="inist">12-0087525</idno>
<date when="2012">2012</date>
<idno type="stanalyst">PASCAL 12-0087525 INIST</idno>
<idno type="RBID">Pascal:12-0087525</idno>
<idno type="wicri:Area/Main/Corpus">002206</idno>
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<seriesStmt><idno type="ISSN">1536-125X</idno>
<title level="j" type="abbreviated">IEEE trans. nanotechnol. </title>
<title level="j" type="main">IEEE transactions on nanotechnology </title>
</seriesStmt>
</fileDesc>
<profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Barrier height</term>
<term>Capacitance</term>
<term>Delay time</term>
<term>Energy dissipation</term>
<term>Gate voltage</term>
<term>Green function</term>
<term>High k dielectric</term>
<term>Indium arsenides</term>
<term>Nanoelectronics</term>
<term>Non equilibrium conditions</term>
<term>Performance evaluation</term>
<term>Quantum effect</term>
<term>Silicon oxides</term>
<term>Switching</term>
<term>Transconductance</term>
<term>Tunnel effect</term>
<term>Voltage threshold</term>
</keywords>
<keywords scheme="Pascal" xml:lang="fr"><term>Evaluation performance</term>
<term>Nanoélectronique</term>
<term>Transconductance</term>
<term>Commutation</term>
<term>Temps retard</term>
<term>Dissipation énergie</term>
<term>Effet tunnel</term>
<term>Hauteur barrière</term>
<term>Capacité électrique</term>
<term>Effet quantique</term>
<term>Seuil tension</term>
<term>Tension de grille</term>
<term>Régime hors équilibre</term>
<term>Fonction Green</term>
<term>Arséniure d'indium</term>
<term>Oxyde de silicium</term>
<term>Diélectrique permittivité élevée</term>
<term>SiO2</term>
</keywords>
</textClass>
</profileDesc>
</teiHeader>
<front><div type="abstract" xml:lang="en">The effects of gate dielectric constant on the performance of a gate all around indium arsenide (InAs) nanowire transistor are studied using a 3-D quantum simulation. The replacement of SiO<sub>2</sub>
 by a high-κ dielectric improves the OFF-state current, the ON-state current, the ON/OFF current ratio, the inverse subthreshold slope, the channel transconductance, and the switching delay and degrades the power-delay product. The OFF-state current is mainly tunneling current and the high-κ gate dielectrics improve the device OFF-state performance by increasing the tunnel barrier length. On the other hand, the ON-state current is mainly thermal current and the high-κ dielectrics improve the device ON-state performance by reducing the barrier height. The gate capacitance is increased with high-κ dielectrics. However, the improved ON-state current with high-κ dielectrics makes the switching delay shorter and increases the power (V<sub>DD</sub>
I<sub>ON</sub>
) dissipation and power-delay product. Due to very small effective mass of electron in InAs, the quantum effect on threshold voltage is strong and the device with smaller cross section shows better ON-OFF and switching performance at the same gate overdrive voltage.</div>
</front>
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<inist><standard h6="B"><pA><fA01 i1="01" i2="1"><s0>1536-125X</s0>
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<fA03 i2="1"><s0>IEEE trans. nanotechnol. </s0>
</fA03>
<fA05><s2>11</s2>
</fA05>
<fA06><s2>1</s2>
</fA06>
<fA08 i1="01" i2="1" l="ENG"><s1>Effects of Dielectric Constant on the Performance of a Gate All Around InAs Nanowire Transistor</s1>
</fA08>
<fA11 i1="01" i2="1"><s1>ALAM (Khairul)</s1>
</fA11>
<fA11 i1="02" i2="1"><s1>ABU ABDULLAH (Md.)</s1>
</fA11>
<fA14 i1="01"><s1>Department of Electrical and Electronic Engineering, East West University</s1>
<s2>Dhaka 1212</s2>
<s3>BGD</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
</fA14>
<fA20><s1>82-87</s1>
</fA20>
<fA21><s1>2012</s1>
</fA21>
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<fA43 i1="01"><s1>INIST</s1>
<s2>27310</s2>
<s5>354000508870670130</s5>
</fA43>
<fA44><s0>0000</s0>
<s1>© 2012 INIST-CNRS. All rights reserved.</s1>
</fA44>
<fA45><s0>30 ref.</s0>
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<fA47 i1="01" i2="1"><s0>12-0087525</s0>
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<fA60><s1>P</s1>
</fA60>
<fA61><s0>A</s0>
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<fA64 i1="01" i2="1"><s0>IEEE transactions on nanotechnology </s0>
</fA64>
<fA66 i1="01"><s0>USA</s0>
</fA66>
<fC01 i1="01" l="ENG"><s0>The effects of gate dielectric constant on the performance of a gate all around indium arsenide (InAs) nanowire transistor are studied using a 3-D quantum simulation. The replacement of SiO<sub>2</sub>
 by a high-κ dielectric improves the OFF-state current, the ON-state current, the ON/OFF current ratio, the inverse subthreshold slope, the channel transconductance, and the switching delay and degrades the power-delay product. The OFF-state current is mainly tunneling current and the high-κ gate dielectrics improve the device OFF-state performance by increasing the tunnel barrier length. On the other hand, the ON-state current is mainly thermal current and the high-κ dielectrics improve the device ON-state performance by reducing the barrier height. The gate capacitance is increased with high-κ dielectrics. However, the improved ON-state current with high-κ dielectrics makes the switching delay shorter and increases the power (V<sub>DD</sub>
I<sub>ON</sub>
) dissipation and power-delay product. Due to very small effective mass of electron in InAs, the quantum effect on threshold voltage is strong and the device with smaller cross section shows better ON-OFF and switching performance at the same gate overdrive voltage.</s0>
</fC01>
<fC02 i1="01" i2="X"><s0>001D03F18</s0>
</fC02>
<fC03 i1="01" i2="X" l="FRE"><s0>Evaluation performance</s0>
<s5>01</s5>
</fC03>
<fC03 i1="01" i2="X" l="ENG"><s0>Performance evaluation</s0>
<s5>01</s5>
</fC03>
<fC03 i1="01" i2="X" l="SPA"><s0>Evaluación prestación</s0>
<s5>01</s5>
</fC03>
<fC03 i1="02" i2="X" l="FRE"><s0>Nanoélectronique</s0>
<s5>02</s5>
</fC03>
<fC03 i1="02" i2="X" l="ENG"><s0>Nanoelectronics</s0>
<s5>02</s5>
</fC03>
<fC03 i1="02" i2="X" l="SPA"><s0>Nanoelectrónica</s0>
<s5>02</s5>
</fC03>
<fC03 i1="03" i2="X" l="FRE"><s0>Transconductance</s0>
<s5>03</s5>
</fC03>
<fC03 i1="03" i2="X" l="ENG"><s0>Transconductance</s0>
<s5>03</s5>
</fC03>
<fC03 i1="03" i2="X" l="SPA"><s0>Transconductancia</s0>
<s5>03</s5>
</fC03>
<fC03 i1="04" i2="X" l="FRE"><s0>Commutation</s0>
<s5>04</s5>
</fC03>
<fC03 i1="04" i2="X" l="ENG"><s0>Switching</s0>
<s5>04</s5>
</fC03>
<fC03 i1="04" i2="X" l="SPA"><s0>Conmutación</s0>
<s5>04</s5>
</fC03>
<fC03 i1="05" i2="X" l="FRE"><s0>Temps retard</s0>
<s5>05</s5>
</fC03>
<fC03 i1="05" i2="X" l="ENG"><s0>Delay time</s0>
<s5>05</s5>
</fC03>
<fC03 i1="05" i2="X" l="SPA"><s0>Tiempo retardo</s0>
<s5>05</s5>
</fC03>
<fC03 i1="06" i2="X" l="FRE"><s0>Dissipation énergie</s0>
<s5>06</s5>
</fC03>
<fC03 i1="06" i2="X" l="ENG"><s0>Energy dissipation</s0>
<s5>06</s5>
</fC03>
<fC03 i1="06" i2="X" l="SPA"><s0>Disipación energía</s0>
<s5>06</s5>
</fC03>
<fC03 i1="07" i2="X" l="FRE"><s0>Effet tunnel</s0>
<s5>07</s5>
</fC03>
<fC03 i1="07" i2="X" l="ENG"><s0>Tunnel effect</s0>
<s5>07</s5>
</fC03>
<fC03 i1="07" i2="X" l="SPA"><s0>Efecto túnel</s0>
<s5>07</s5>
</fC03>
<fC03 i1="08" i2="X" l="FRE"><s0>Hauteur barrière</s0>
<s5>08</s5>
</fC03>
<fC03 i1="08" i2="X" l="ENG"><s0>Barrier height</s0>
<s5>08</s5>
</fC03>
<fC03 i1="08" i2="X" l="SPA"><s0>Altura barrera</s0>
<s5>08</s5>
</fC03>
<fC03 i1="09" i2="X" l="FRE"><s0>Capacité électrique</s0>
<s5>09</s5>
</fC03>
<fC03 i1="09" i2="X" l="ENG"><s0>Capacitance</s0>
<s5>09</s5>
</fC03>
<fC03 i1="09" i2="X" l="SPA"><s0>Capacitancia</s0>
<s5>09</s5>
</fC03>
<fC03 i1="10" i2="X" l="FRE"><s0>Effet quantique</s0>
<s5>10</s5>
</fC03>
<fC03 i1="10" i2="X" l="ENG"><s0>Quantum effect</s0>
<s5>10</s5>
</fC03>
<fC03 i1="10" i2="X" l="SPA"><s0>Efecto cuántico</s0>
<s5>10</s5>
</fC03>
<fC03 i1="11" i2="X" l="FRE"><s0>Seuil tension</s0>
<s5>11</s5>
</fC03>
<fC03 i1="11" i2="X" l="ENG"><s0>Voltage threshold</s0>
<s5>11</s5>
</fC03>
<fC03 i1="11" i2="X" l="SPA"><s0>Umbral tensión</s0>
<s5>11</s5>
</fC03>
<fC03 i1="12" i2="X" l="FRE"><s0>Tension de grille</s0>
<s5>12</s5>
</fC03>
<fC03 i1="12" i2="X" l="ENG"><s0>Gate voltage</s0>
<s5>12</s5>
</fC03>
<fC03 i1="12" i2="X" l="SPA"><s0>Voltaje de rejilla</s0>
<s5>12</s5>
</fC03>
<fC03 i1="13" i2="X" l="FRE"><s0>Régime hors équilibre</s0>
<s5>13</s5>
</fC03>
<fC03 i1="13" i2="X" l="ENG"><s0>Non equilibrium conditions</s0>
<s5>13</s5>
</fC03>
<fC03 i1="13" i2="X" l="SPA"><s0>Régimen fuera equilibrio</s0>
<s5>13</s5>
</fC03>
<fC03 i1="14" i2="X" l="FRE"><s0>Fonction Green</s0>
<s5>14</s5>
</fC03>
<fC03 i1="14" i2="X" l="ENG"><s0>Green function</s0>
<s5>14</s5>
</fC03>
<fC03 i1="14" i2="X" l="SPA"><s0>Función Green</s0>
<s5>14</s5>
</fC03>
<fC03 i1="15" i2="3" l="FRE"><s0>Arséniure d'indium</s0>
<s2>NK</s2>
<s5>22</s5>
</fC03>
<fC03 i1="15" i2="3" l="ENG"><s0>Indium arsenides</s0>
<s2>NK</s2>
<s5>22</s5>
</fC03>
<fC03 i1="16" i2="3" l="FRE"><s0>Oxyde de silicium</s0>
<s2>NK</s2>
<s5>23</s5>
</fC03>
<fC03 i1="16" i2="3" l="ENG"><s0>Silicon oxides</s0>
<s2>NK</s2>
<s5>23</s5>
</fC03>
<fC03 i1="17" i2="X" l="FRE"><s0>Diélectrique permittivité élevée</s0>
<s5>24</s5>
</fC03>
<fC03 i1="17" i2="X" l="ENG"><s0>High k dielectric</s0>
<s5>24</s5>
</fC03>
<fC03 i1="17" i2="X" l="SPA"><s0>Dieléctrico alta constante dieléctrica</s0>
<s5>24</s5>
</fC03>
<fC03 i1="18" i2="X" l="FRE"><s0>SiO2</s0>
<s4>INC</s4>
<s5>82</s5>
</fC03>
<fC07 i1="01" i2="X" l="FRE"><s0>Composé IV-VI</s0>
<s5>15</s5>
</fC07>
<fC07 i1="01" i2="X" l="ENG"><s0>IV-VI compound</s0>
<s5>15</s5>
</fC07>
<fC07 i1="01" i2="X" l="SPA"><s0>Compuesto IV-VI</s0>
<s5>15</s5>
</fC07>
<fN21><s1>065</s1>
</fN21>
<fN44 i1="01"><s1>OTO</s1>
</fN44>
<fN82><s1>OTO</s1>
</fN82>
</pA>
</standard>
</inist>
</record>

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Effects of Dielectric Constant on the Performance of a Gate All Around InAs Nanowire Transistor

Effects of Dielectric Constant on the Performance of a Gate All Around InAs Nanowire Transistor

Descripteurs français

English descriptors

Abstract

Links toward previous steps (curation, corpus...)

Links to Exploration step

Le document en format XML

Pour manipuler ce document sous Unix (Dilib)

Pour mettre un lien sur cette page dans le réseau Wicri